1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method.
2. Related Background Art
Recently, a high performance LSI is increasingly desired. A transistor is miniaturized for higher performance of LSI. Because of the miniaturization of the transistor, the channel length becomes shorter and the switching speed of the transistor is improved. This leads to improvement in signal processing speed of the transistor.
Accompanying such transistor miniaturization, a gate insulative film is required to be formed thinner. It is anticipated that a gate insulative film having a thickness of equal to or less than 1 nm is required in the future. In the case where a silicon oxide film is used as the gate insulative film, when the silicon oxide film is made thinner to equal to or less than 1 nm, direct tunnel current penetrating the film becomes dominant and the reliability of the gate insulative film becomes deteriorated. In order to cope with that, conventionally, attempts to use a material having larger dielectric constant than the silicon oxide film, the so-called high-k material as the gate insulative film have been made.
However, the high-k material has low heat resistance and poor compatibility to the conventional semiconductor manufacturing process. For example, in the case where the high-k material is used as the gate insulative film, because many of the high-k materials are metal oxide, SiO2 or silicate is formed at the interface between the high-k material and the silicon substrate. Because of this interfacial reaction, it is very difficult to form the high-k material having an oxide film reduced thickness (hereinafter, referred to as EOT (Equivalent Oxide Thickness)) of equal to or less than 1 nm on the silicon substrate at present.
Accordingly, in order to avoid the interfacial reaction, a semiconductor device using a gate insulative film including a multilayer film of silicon nitride film and silicon oxide film (hereinafter, also referred to as “ON multilayer film”) is known (see Publication of Japanese Patent Application No. 2002-83960 (hereinafter, referred to as “Patent Document 1”)
When the ON multilayer film is adopted in place of the high-k material, the interfacial reaction between the silicon substrate and the gate insulative film can be suppressed. However, since the dielectric constant of the ON multilayer film is lower than that of the high-k material, the EOT of the entire gate insulative film rises. In the patent document 1, a semiconductor manufacturing process for reducing the EOT of the gate insulative film while using the ON multilayer film for the gate insulative film is disclosed.
However, by the semiconductor manufacturing process disclosed in the patent document 1, the EOT of the gate insulative film can not be reduced sufficiently. Further, since suitable process conditions are not disclosed in the document, the thickness of the gate insulative film can not be formed uniformly. In case that a silicon nitride film is formed at high temperature, if the physical thickness of the gate insulative film becomes equal to or less than 2 nm, non-uniformity of the thickness of a few atom layers occurs. This non-uniformity of the thickness causes non-uniformity of the threshold voltage, because the non-uniformity of the thickness causes variability of a silicon oxide film which is formed by oxidation of the silicon nitride film. This leads to reliability deterioration of the semiconductor device. The problem about non-uniformity of the silicon nitride film is also pointed out in D. Matshushita, et al., Jpn. J. Appl. Phys. 40(2001) p2827 (hereinafter, referred to as “Non-patent Document 1”).